RISC-V Instruction Encoding

Instructions

Write a C program that reads a string with a RISC-V instruction from STDIN, parses its content in a way of obtaining its fields, packs the instruction's fields in a 32 bit value and writes the hexadecimal representation of the instruction to STDOUT.

The code snippet below can be used to compare strings as standard C libraries such as string.h are not available in the simulator. It is similar to string.h's strcmp but it has the number of characters to be compared as a parameter.

int strcmp_custom(char *str1, char *str2, int n_char){
    for (int i = 0; i < n_char; i++){
        if (str1[i] < str2 [i])
            return -1;
        else if (str1[i] > str2 [i])
            return 1;
    }
    return 0;
}

The set of instructions that need to be encoded by your program is presented in the table below, alongside its opcode, instruction type and other fields (e.g. funct3 and funct7) if applicable.

Instruction	Inst Syntax	Inst Type	OPCODE	FUNCT3	FUNCT7
lui	lui rd, imm	U	0110111	N/A	N/A
auipc	auipc rd, imm	U	0010111	N/A	N/A
jal	jal rd, imm	J	1101111	N/A	N/A
jalr	jalr rd, imm(rs1)	I	1100111	000	N/A
beq	beq rs1, rs2, imm	B	1100011	000	N/A
bne	bne rs1, rs2, imm	B	1100011	001	N/A
blt	blt rs1, rs2, imm	B	1100011	100	N/A
bge	bge rs1, rs2, imm	B	1100011	101	N/A
bltu	bltu rs1, rs2, imm	B	1100011	110	N/A
bgeu	bgeu rs1, rs2, imm	B	1100011	111	N/A
lb	lb rd, imm(rs1)	I	0000011	000	N/A
lh	lh rd, imm(rs1)	I	0000011	001	N/A
lw	lw rd, imm(rs1)	I	0000011	010	N/A
lbu	lbu rd, imm(rs1)	I	0000011	100	N/A
lhu	lhu rd, imm(rs1)	I	0000011	101	N/A
sb	sb rs2, imm(rs1)	S	0100011	000	N/A
sh	sh rs2, imm(rs1)	S	0100011	001	N/A
sw	sw rs2, imm(rs1)	S	0100011	010	N/A
addi	addi rd, rs1, imm	I	0010011	000	N/A
slti	slti rd, rs1, imm	I	0010011	010	N/A
sltiu	sltiu rd, rs1, imm	I	0010011	011	N/A
xori	xori rd, rs1, imm	I	0010011	100	N/A
ori	ori rd, rs1, imm	I	0010011	110	N/A
andi	andi rd, rs1, imm	I	0010011	111	N/A
slli	slli rd, rs1, imm**	I	0010011	001	0000000*
srli	srli rd, rs1, imm	I	0010011	101	0000000*
srai	srai rd, rs1, imm	I	0010011	101	0100000*
add	add rd, rs1, rs2	R	0110011	000	0000000
sub	sub rd, rs1, rs2	R	0110011	000	0100000
sll	sll rd, rs1, rs2	R	0110011	001	0000000
slt	slt rd, rs1, rs2	R	0110011	010	0000000
sltu	sltu rd, rs1, rs2	R	0110011	011	0000000
xor	xor rd, rs1, rs2	R	0110011	100	0000000
srl	srl rd, rs1, rs2	R	0110011	101	0000000
sra	sra rd, rs1, rs2	R	0110011	101	0100000
or	or rd, rs1, rs2	R	0110011	110	0000000
and	and rd, rs1, rs2	R	0110011	111	0000000

* slli, srli and srai are type I instructions but its immediate takes up only 5 bits, the remaining 7 bits are filled with a funct7 value.
** The imm field may also appear as shamt, which stands for shift amount.

Input

RV32I assembly instruction string with at most 40 bytes. There will be no pseudo-instructions, the registers will be referenced with their x-name (e.g. x2, x10), and immediate values will be in decimal.

Output

The 32 bit encoded instruction in its Big Endian hexadecimal representation (hex_code() from the previous exercise can be used).

Examples

Test Case	Input	Output
1	lb x10, 4(x9)	0x00448503
2	and x31, x20, x25	0x019A7FB3
3	slti x12, x13, -1	0xFFF6A613
4	bge x7, x0, 256	0x1003D063
5	jalr x1, -32(x9)	0xFE0480E7

Notes and Tips

This exercise depends on some things used in Exercise 5.1, such as hex_code() and pack() functions, so it is recommended to do Exercise 5.1 first.
You can use this base code as a starting point, or build your solution from scratch if you want.
Refer to the RISC-V Instruction Set Manual to check how each instruction is encoded. Especially, consult the RV32I Base Instruction Set in Table 19.2, presented in Chapter 19. For information regarding the encoding of immediates, check Figures 2.3 and 2.4 in Section 2.3 .
You can test your code using the simulator's assistant from this link.